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[1]何 全,陈忠学,章国豪.基于RF SOI CMOS工艺高线性低功耗LNA设计[J].电子设计工程,2017,(17):111-114.
 HE Quan,CHEN Zhong-xue,ZHANG Guo-hao.A high-linearity and low-power LNA in RF SOI CMOS technology[J].SAMSON,2017,(17):111-114.
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基于RF SOI CMOS工艺高线性低功耗LNA设计(PDF)
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《电子设计工程》[ISSN:1674-6236/CN:61-1477/TN]

卷:
期数:
2017年17期
页码:
111-114
栏目:
微处理器
出版日期:
2017-09-05

文章信息/Info

Title:
A high-linearity and low-power LNA in RF SOI CMOS technology
文章编号:
1674-6236(2017)17-0111-04
作者:
何 全1陈忠学12章国豪1
(1. 广东工业大学 广东 广州 510006;2. 广州钧衡微电子科技有限公司 广东 广州 510006)
Author(s):
HE Quan1 CHEN Zhong-xue12 ZHANG Guo-hao1
(1. Guangdong University of Technology,Guangzhou 510006, China; 2. Guangzhou Junheng Micro-Electrics Tech Ltd.,Guangzhou 510006, China )
关键词:
SOI 低噪声放大器 高线性 低功耗 S波段
Keywords:
SOI low noise amplifier high-linearity low-power S band
分类号:
TN722.3
DOI:
-
文献标志码:
A
摘要:
基于IBM公司的0.18 μm RF SOI CMOS工艺,设计了一款应用于S波段的高线性低功耗低噪声放大器。在传统共源共栅拓扑结构的基础上,本文提出使用有源偏置电路、级间匹配网络和并联反馈结构,使设计的放大器具有噪声低、线性度高和功耗小等特点。仿真结果表明,该放大器在2.3 ~2.7 GHz频段,电源电压为1.8 V,功耗为9.8 mW的条件下,噪声系数小于0.8 dB,增益大于14 dB,输入回波损耗和输出回波损耗均大于10 dB,隔离度大于27 dB,输入三阶交调截取点大于15 dBm, 满足无线基础架构接收器对低噪声放大器的所有性能要求。
Abstract:
A high-linearity and low-power low noise amplifier was implemented in IBM’s 0.18 μm RF SOI CMOS technology for S band application. Based on conventional cascode topological structure, this improved LNA achieves high linearity, low noise and low power while using an active bias circuit combined with inter-stage matching network and a parallel feedback structure. The SOI CMOS LNA has a simulated noise figure of less than 0.8 dB, gain of greater than 14 dB, input return loss and output return loss of more than 10 dB, reverse isolation of more than 27 dB, input third order intercept point of more than 15 dBm over 2.3 to 2.7 GHz under the conditions that the power supply voltage is 1.8 V and the power dissipation is 9.8 mW, satisfying all the need for LNA in wireless receivers.

参考文献/References:

[1] 张胜标,张志浩,章国豪. 用于S波段的高线性低噪声放大器[J]. 电子器件, 2016,39(1):57-61.[2] Thomas H. Lee.CMOS射频集成电路设计[M].2版.余志平,周润德,等译. 北京:电子工业出版社,2012.[3] 高向可. C波段低噪声放大器的仿真设计[J]. 电子设计工程, 2011,19(22):94-97.[4] 方方. 基于ADS的C波段的低噪声放大器仿真设计研究[J]. 电子设计工程, 2013,21(1):67-69.[5] Hassan M, Olson C, Kovac D, et al. An Envelope-Tracking CMOS-SOS Power Amplifier With 50% Overall PAE and 29.3 dBm Output Power for LTE Applications[C]// 2012 IEEE Compound Semiconductor Integrated Circuit Sym-posium(CSICS).La Jolla, CA:IEEE,2012:14-17.[6] 林俊明,郑耀华,郑瑞青,等. 应用于移动手机的SOI线性射频功率放大器的设计[J]. 电子技术应用, 2015,41[9]:60-62.[7] Madan A, Mcpartlin M J, Masse C, et al. A 5 GHz 0.95 dB NF Highly Linear Cascode Floa-ting-Body LNA in 180 nm SOI CMOS Technology [J]. IEEE Microwave and Wireless Components Letters, 2012,22(4):200-20.[8] 郑直. SOI功率器件的新结构研究[D]. 成都: 电子科技大学, 2013.[9] Moezzi M, Bakhtiar S. Wideband LNA Using Active Inductor With Multiple Feed-Forward Noise Reduction Paths[J]. IEEE Transactions on Micro-wave Theory and Techniques, 2012,60(4):1069-1078.[10]刘祖华,刘斌,黄亮,等. 应用于WLAN的低噪声放大器及射频前段的设计[J]. 电子技术应用,2014,40(1):38-40.[11]Razavi B. RF Microelectronics[M]. New York: Prentice Hall, 2011.[12]Arshad S, Ramzan R, Zafar F, et al. Highly linear inductively degenerated 0.13μm CMOS LNA using FDC technique[C]// 2014 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS). Ishigaki : IEEE, 2014: 225-228.[13]Thacker M B, Awakhare M, Khobragade R H, et al. Multi-Standard Highly Linear CMOS LNA[C]// 2014 International conference on Electronic System, Signal Processing and Computing Techno-logies. Nagpur: IEEE, 2014:63-68.[14]IJI A, Xi Zhu, Heimlich M. A 3-5 GHz LNA in 0.25μm SOI CMOS Process for Implantable WBANs [C]// 2012 IEEE 55th International Midwest Symposium on Circuits and Systems(MWSCAS). Boise ID, IEEE, 2012:766-769.[15]Hossein N, Miles S, Naveen Y, et al. A 0.8dB NF, 4.6dBm IIP3, 4.6dB IIP3, 1.8-2.2GHz,Low-Power LNA in 130 nm RF SOI CMOS Technology[C]//Wireless and Microwave Circuits and Systems(WMCS). Waco, TX: IEEE, 2015: 1-4.

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备注/Memo

备注/Memo:
收稿日期:2016-07-25 稿件编号:201607175基金项目:广东省战略新兴产业重大专项(2012A010701002)作者简介:何 全(1990—),男,湖北荆州人,硕士研究生。研究方向:射频与微波集成电路设计。
更新日期/Last Update: 2017-09-06