|本期目录/Table of Contents|

[1]张 婷,钟传杰.一种用于音频的2-2级联结构Sigma-Delta调制器设计[J].电子设计工程,2017,(17):124-128.
 ZHANG Ting,ZHONG Chuan-jie.A 2-2 mash Sigma-Delta modulator design for audio application[J].SAMSON,2017,(17):124-128.
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一种用于音频的2-2级联结构Sigma-Delta调制器设计(PDF)
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《电子设计工程》[ISSN:1674-6236/CN:61-1477/TN]

卷:
期数:
2017年17期
页码:
124-128
栏目:
微处理器
出版日期:
2017-09-05

文章信息/Info

Title:
A 2-2 mash Sigma-Delta modulator design for audio application
文章编号:
1674-6236(2017)17-0124-05
作者:
张 婷钟传杰
(江南大学 物联网工程学院, 江苏 无锡 214122)
Author(s):
ZHANG TingZHONG Chuan-jie
(School of Internet of Things Engineering, Jiangnan University,Wuxi 214122,China)
关键词:
音频 低功耗 Sigma-Delta调制器 运算放大器
Keywords:
audio low power consumption Sigma-Delta modulator operational amplifier
分类号:
TN47
DOI:
-
文献标志码:
A
摘要:
基于csmc0.35μm CMOS工艺,设计了一种用于音频设备的低功耗Sigma-Delta调制器,该调制器采用四阶噪声整形2-2级联结构实现,在获得高动态范围和高精度的同时更能够保证系统的稳定性。运算放大器采用两级全差分电路结构,仿真结果表明,运放的直流开环增益为90.9 dB,在3.3 V电源电压下,信号带宽为20 kHz,过采样率为64时,信噪比为101.45 dB,有效位数达到了16 bit,调制器功耗约为7.8 mW。
Abstract:
In this paper, A low-power 2-2 multi stage noise shaping (MASH) Sigma-Delta analog to digital modulator for audio application is implemented. The design was fabricated in a 0.35 μm CMOS process. In order to reduce power consumption, fully differential two stage operational amplifiers are used. The simulation shows that the DC open loop gain is up to 90.9 dB.When the power is 3.3 V and OSR is 64, the simulation results show that SNDR of the modular can reach 101.45 dB,while the power consumption is merely 7.8 mW.

参考文献/References:

[1] YANG Shou-jun, TONG Zi-quan, JIANG Yu-ming. The design of a muti-bit sigma-delta ADC modulator[C]// International Conference on Measu-rement, Information and Control. Harbin:[s.n.], 2013:280-283.[2] Koli K, Kallioinen S, Jussila J, et al. A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS[J]. IEEE Solid-state circuits, 2010,45(12):2807-2810.[3] Souri K, Chae Y, Makinwa K. A CMOS temp-erature sensor with a voltage-calibrated inaccuracy of ±0.15℃(3σ)from-55 to 125℃[J].IEEE Journal Solid-State Circuits, 2013,48(1):292-301.[4] WU Hai-jun, Li Bin, ZHANG Hua-bin. A 1.2V power adaptable 95-to-67 dB DR 2-2 mash delta-sigma ADC with configurable OSR[C]// Electron Devices and Solid-State Circuits, Hong Kong, 2013,12(1):1-2.[5] Xie H L, Rakers P, Femandez R, et al. Single-Chip Multi-band SAW-less LTE WCDMA and EGPRS CMOS Receiver with Diversity[J]. IEEE Radio Frequency Integrated Circuits Sympo-sium,2011,60(5):1-4.[6] GE Bin-jie, WANG Xin-an, ZHANG Xing, et al. Sigma-delta modulator modeling analysis and design[J]. Semicond, 2010,31(9):198-202.[7] Agah A, Vleugels K, Griffin P B, et al. A high-resolution low-power incremental Σ-Δ ADC with extended range for biosensor arrays[J]. IEEE J Solid-State Circuits, 2010,45(6):1099.[8] GE Bin-jie, WANG Xin-an, ZHANG Xing, et al. Study and analysis of coefficient mismatch in MASH21 sigma-delta modulator[J]. Semicond, 2010,31(1):015007-1-4.[9] Seo M W, Suh S H, Iida T, et al. A low-noise high intrascene dynamic range CMOS image sensor with a 12 to 19b variable-resolution column-parallel folding-integration/cyclic ADC[J]. IEEE Journal of Solid-State Circuits, 2012,47(1):272-283.[10]CAI Chen-yan, YANG Jiang, SUN Sai-weng, et al. A passive excess-loop-delay compensation technique for gm-C based continuous-time ΔΣ modulators[C]//Circuits and Systems(MWSCAS), 2011 IEEE 54th International Midwest Symposium. Seoul, 2011:1-4.[11]Chae Y, Cheon J, Lim S, et al. A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel ADC arachitecture[J]. IEEE Journal of Solid-State Circuits, 2011, 46(1):236-247.[12]李亮,陈海珍. 应用于数字音频的二阶Sigma-Delta调制器设计[J]. 微电子学与计算机, 2010,27(7): 198-201.[13]Liang J, Johns D A. A frequency-scalable 15-bit incremental ADC for low power sensor applica-tion[C]//Proceeding of International Symposium on Circuits and Systems(ISCAS), IEEE, 2010:2418-2412.[14]Shin S K, Rudell J C, Daly D C, et al. A12bit 200MS/s zero-crossing-based pipelined ADC with early Sub-ADC decision and output residue background calibration[J]. IEEE Journal of Solid-State Circuits, 2014,49(6):1366-1382.[15]Shafti A, Yavari M. A zero-crossing based 10 bit 100MS/s pipeline ADC with controlled current in 90 nm CMOS[J]. Analog Integrated Circuits and Signal Processing, 2014, 80(1):141-145.

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备注/Memo

备注/Memo:
收稿日期:2016-07-22 稿件编号:201607162作者简介:张 婷(1990—),女,江苏宿迁人,硕士研究生。研究方向:集成电路设计。
更新日期/Last Update: 2017-09-07